Passive electrical devices, such as capacitors or inductors, are sometimes integrated with complementary metal-oxide-semiconductor (“CMOS”) chips. Traditionally, when large capacitances or inductances are required, the use of large size passive devices is necessary. As a result, interconnecting such devices is only possible through external electrical paths, such as wire bonding. Moreover, when working with larger chip sizes, longer electrical paths are necessary.
Traditional passive device/CMOS integration presents a number of disadvantages. First, electrical parasitics created by longer electrical paths can deteriorate chip performance, especially after molding. Second, it is difficult to shrink the size of the system due to the pads required to wirebond the passive devices to the CMOS chip. Third, because the passive devices must be individually bonded to the CMOS chip, precision is decreased which further increases difficulty of system shrinkage. Fourth, precise assembly of multiple passive devices with a CMOS chip takes effort, which increases fabrication costs.